The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to a method and structure for isolating devices such as metal oxide silicon (MOS) field effect transistors, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as bipolar transistors, complementary metal oxide semiconductor (CMOS) field effect transistors, bipolar complementary metal oxide semiconductor (BiCMOS) field effect transistors, among others.
Industry utilizes or has proposed techniques for isolating devices in an integrated circuit device. An example of a technique is the local oxidation of silicon (LOCOS) as defined in U.S. Pat. No. 3,970,486, assigned to U.S. Philips Corp. The LOCOS technique generally includes steps of forming a thin silicon dioxide layer (SiO.sub.2) (or pad oxide layer) overlying a silicon substrate. A layer of silicon nitride is formed overlying the silicon dioxide layer. A step of patterning the silicon nitride (Si.sub.3 N.sub.4) layer to expose portions of the pad oxide is performed. The exposed portions of the pad oxide define regions for field isolation oxide. Using the silicon nitride as a mask, a step of thermal oxidation forms field isolation oxide regions in the exposed pad oxide regions.
A limitation with the LOCOS technique is certain undesirable effects caused by lateral oxidation of silicon dioxide occurs as illustrated by FIG. 1. In particular, the lateral oxidation of silicon dioxide often causes an undesirable "bird's beak" type structure. As shown, FIG. 1 illustrates a conventional field isolation oxide structure 10 including a semiconductor substrate 11, a field isolation oxide region 13, an active region 17, and a bird's beak type structure 15. As shown, the bird's beak type structure prevents formation of devices in active regions because of thickness 19.
Various techniques have been proposed to overcome the undesirable effects of the bird's beak type structure. In particular, formation of a thinner oxide layer often creates a shorter bird's beak length. A thicker nitride layer also creates a shorter bird's beak length. But such techniques induce more crystal defects to the silicon substrate or the like. The crystalline defects increase resistance in the substrate, thereby causing switching problems or the like. The thinner bird's beak type structure also causes electrical current leakage between adjacent devices, by not effectively isolating such devices.
Another technique has been proposed to provide a thicker oxide layer to create a thicker bird's beak type structure. The thicker bird's beak type structure tends to prevent electric leakage between devices. But the thicker bird's beak type structure causes a longer bird's beak, that is, a bird's beak which protrudes further into the active device region. The longer bird's beak structure also reduces packing density of integrated circuits, which is clearly an undesirable result.
Still another technique uses a "poly-buffered" LOCOS method. The poly-buffered LOCOS method relies upon a multi-layered sandwich structure including an oxide layer, a polysilicon layer, and a nitride layer. The poly-buffered LOCOS method reduces lateral encroachment of silicon dioxide. But the poly-buffered LOCOS method creates a second bird's beak type structure as illustrated by FIG. 2. As shown, FIG. 2 illustrates conventional field isolation oxide regions 20 made by way of the conventional poly-buffered LOCOS method. The conventional method provides a semiconductor substrate field isolation oxide regions 23, a first bird's beak type structure 25, and a second bird's beak type structure 29. Another limitation with the poly-buffered LOCOS method includes polysilicon etching residues 27 remaining on edges of the field isolation oxide regions. The second bird's beak type structure and etching residues are clearly undesirable results.
From the above it is seen that a method of fabricating a semiconductor isolation region that is easy, cost effective, and reliable is often desired.